A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI

Fukashi MORISHITA  Hideyuki NODA  Isamu HAYASHI  Takayuki GYOHTEN  Mako OKAMOTO  Takashi IPPOSHI  Shigeto MAEGAWA  Katsumi DOSAKA  Kazutami ARIMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.4    pp.765-771
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.765
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
SOI,  capacitorless,  DRAM,  low power,  data retention,  

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We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2 Mb test device has been fabricated on 130 nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1 ns row-access time is achieved and 250 MHz operation can be realized by using 2 bank 8 b-burst mode.