A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's

Fayez Robert SALIBA
Takayasu SAKURAI

IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.4    pp.743-748
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.743
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
active leakage,  low power,  SRAM,  

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We report an SRAM with a 90% reduction of active-leakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells, the wordline voltage is controlled so that it is always lower than the supply voltage in the proposed SRAM, with a self-alignment timing generator. The additional area overhead of the timing generator is 3.5%.