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The Front-End LSI with a 5-Tap PRML for 2 Reading and Writing of BD-R/RW/ROM
GoangSeog CHOI JumHan BAE HyunSoo PARK
IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
BD, LSI, PRML, OPC, Viterbi detector,
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The front-end LSI having a capable of 2 reading and writing of BD-R/RW/ROM is developed. Its readability is improved by adopting 5-tap adaptive partial response maximum likelihood (PRML) with the PR(a,b,c,d,e) type channel. Due to the proposed PRML, less than 210-4 of the bit error rate (BER) is achieved with radial and tangential tilt margin of over 0.6°on 25 GB disc. The method of an optimum power control (OPC) for stable writing of various BD-R/RW is proposed. The presented chip contains 14-million transistors in a 60 mm2 dies, and is fabricated in 0.18 µm CMOS technology.