Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias

Yoshihide KOMATSU  Koichiro ISHIBASHI  Makoto NAGATA  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.4   pp.692-698
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.692
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
substrate noise,  random variability,  forward body bias,  self adjusted,  impurities,  latch-up,  CMOS,  SoC,  

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This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130 nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability σ (Ids) by 23.2-57.9%.