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Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of LowPower and HighSpeed Operations
Masao MORIMOTO Makoto NAGATA Kazuo TAKI
Publication
IEICE TRANSACTIONS on Electronics
Vol.E90C
No.4
pp.675682 Publication Date: 2007/04/01
Online ISSN: 17451353
DOI: 10.1093/ietele/e90c.4.675
Print ISSN: 09168516 Type of Manuscript: Special Section PAPER (Special Section on LowPower, HighSpeed LSIs and Related Technologies) Category: Digital Keyword: ASDMDL, differential logic, highspeed logic, lowpower logic,
Full Text: PDF(567.1KB)>>
Summary:
Asymmetric Slope Dual Mode Differential Logic (ASDMDL) embodies highspeed dynamic and lowpower static operations in a single design. Twophase dualrail logic signaling is used in a highspeed operation, where a logical evaluation is preceded by precharge, and it asserts one of the rails with an asymmetrically shortened rise transition to express a binary result. On the other hand, singlephase differential logic signaling eliminates precharge and leads to a lowpower static operation. The operation mode is defined by the logic signaling styles, and no control signal is needed in the logic cell. The design of mixed CMOS and ASDMDL logic circuits can be automated with general logic synthesis and placeandroute techniques, since the physical ASDMDL cell is prepared in such a way to comply with a CMOS standardcell design flow. A mixed ASDMDL/CMOS microprocessor in a 0.18µm CMOS technology demonstrated 232 MHz operation, corresponding to 14% speed improvement over a full CMOS implementation. This was achieved by substituting ASDMDL cells for only 4% of the CMOS logic cells in data paths. The lowspeed operation of ASDMDL at 100 MHz was nearly equivalent to that of CMOS. However, power consumption was reduced by 3% due to the use of ASDMDL complex logic cells. Area overhead was less than 4%.

