A Test Structure to Analyze Electrical CMOSFET Reliabilities between Center and Edge along the Channel Width

Takashi OHZONE
Kiyotaka KOMOKU
Toshihiro MATSUDA
Hideyuki IWATA

IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.2    pp.515-522
Publication Date: 2007/02/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.2.515
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
CMOSFET,  reliability,  LDD-type,  channel width,  isolation,  

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A test structure to separately analyze the location where the hot-carrier-induced CMOSFET reliability is determined around the center or the isolation-edge along the channel-width was proposed and fabricated. The test structure has four kinds of MOSFETs; [A] and [D] MOSFETs with a short and a long channel-length all over the channel width, respectively, [B] MOSFET with the short and the long channel-length around the center and the both isolation-edges, respectively, and [C] MOSFET with the channel-length regions vice versa to the [B] MOSFET. The time dependent changes of the threshold voltages VT, the saturation currents IS, the linear currents IL and the maximum transconductances β up to 50,000 s were measured. All data for the wide channel-width MOSFETs were almost categorized into three; [A], [B]/[C] and [D]. The [B]/[C] data were well estimated from simple theoretical discussions by the combination of [A] and [D] data, which mean that the reliabilities are nearly the same around the center or the isolation-edge for the CMOSFETs.