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CMOS Level Converter with Balanced Rise and Fall Delays
Min-su KIM Young-Hyun JUN Sung-Bae PARK Bai-Sun KONG
IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
level converter, voltage scaling, clock, low power,
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A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90 nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.