A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution

Chang-Kyung SEONG
Seung-Woo LEE
Woo-Young CHOI

IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.1    pp.165-170
Publication Date: 2007/01/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.1.165
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
dual-loop clock and data recovery (CDR),  phase interpolator,  phase resolution,  

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A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm2 and consumes 17.8 mW.