A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology

Hideaki KURATA  Satoshi NODA  Yoshitaka SASAGO  Kazuo OTSUGA  Tsuyoshi ARIGANE  Tetsufumi KAWAMURA  Takashi KOBAYASHI  Hitoshi KUME  Kazuki HOMMA  Teruhiko ITO  Yoshinori SAKAMOTO  Masahiro SHIMIZU  Yoshinori IKEDA  Osamu TSUCHIYA  Kazunori FURUSAWA  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.11   pp.2146-2156
Publication Date: 2007/11/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.11.2146
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
flash memory,  multilevel,  inversion-layer-bit-line,  AG-AND,  

Full Text: PDF(2.3MB)>>
Buy this Article

A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.