A 10 b 200 MS/s 1.8 mm2 83 mW 0.13 µm CMOS ADC Based on Highly Linear Integrated Capacitors

Young-Ju KIM  Young-Jae CHO  Doo-Hwan SA  Seung-Hoon LEE  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.10   pp.2037-2043
Publication Date: 2007/10/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.10.2037
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
ADC,  CMOS,  3-D symmetric layout,  low power,  low voltage,  

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This work proposes a 10 b 200 MS/s 1.8 mm2 83 mW 0.13 µm CMOS ADC based on highly linear integrated capacitors for high-quality video system applications such as next-generation DTV and radar vision and wireless communication system applications such as WLAN, WiMax, SDR, LMDS, and MMDS simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC optimizes chip area and power dissipation at the target resolution and sampling rate. The proposed ADC employs two versions of the SHA with gate-bootstrapped NMOS switches and conventional CMOS switches to verify and compare the input sampling effectiveness. Both of the two versions of the wide-band low-noise SHA maintain 10 b input accuracy at 200 MS/s. The proposed all signal-isolated 3-D completely symmetric capacitor layout reduces the device mismatch of two MDACs by isolating each unit capacitor from all neighboring signal lines with all the employed metal lines and by placing extra internal metal lines with a fixed internal bias voltage between signal lines connecting the bottom plate of each unit capacitor. The low-noise on-chip current and voltage references with internal RC filters can select optional off-chip voltage references. The prototype ADC is implemented in a 0.13 µm 1P8M CMOS process. The measured DNL and INL are within 0.24 LSB and 0.35 LSB while the ADC shows a maximum SNDR of 54 dB and 48 dB and a maximum SFDR of 67 dB and 61 dB at 200 MS/s and 250 MS/s, respectively. The ADC with an active die area of 1.8 mm2 consumes 83 mW at 200 MS/s and at a 1.2 V supply.