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Preliminary Demonstration of 1.0 V CMOS Imager with Semi-Pixel-Level ADC Based on Pulse-Width-Modulation Pixel Readout
Keiichiro KAGAWA Makoto SHOUHO Kazuo HASHIGUCHI Masahiro NUNOSHITA Jun OHTA
IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on VLSI Technology toward Frontiers of New Market)
CMOS imager, low voltage, pulse width modulation, ADC,
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We demonstrate low-voltage operation of a CMOS imager with an in-pixel large-gain comparator without degradation of the dynamic range by using a pulse-width-modulation scheme in pixel readout. Experimental results showed a dynamic range of 57 dB with a 1.0 V power supply voltage at the pixel array block, which demonstrates the possibility of low-voltage, single-power-supply operation of imagers fabricated with deep-submicron CMOS technologies.