VLSI Implementation of a 44-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic

Yasuhiro TAKAHASHI  Toshikazu SEKINE  Michio YOKOYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.10   pp.2002-2006
Publication Date: 2007/10/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.10.2002
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: 
Keyword: 
adiabatic logic,  multiplier,  low power,  two-phase power supply,  

Full Text: PDF>>
Buy this Article




Summary: 
An adiabatic logic is a technique to design low power digital VLSI's. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 44-bit 2PADCL multiplier fabricated in a 1.2 µm CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800 kHz. The total power dissipation of the 44-bit 2PADCL multiplier was also 5.19 mW at the 1.5 V DC power supply voltage.