Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems


IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.10    pp.1983-1991
Publication Date: 2007/10/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.10.1983
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Design Technology
soft error,  reliability,  estimation,  computer systems,  instruction-set simulation,  

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This paper proposes a soft-error model for accurately estimating reliability of a computer system at the architectural level within reasonable computation time. The architectural-level soft-error model identifies which part of memory modules are utilized temporally and spatially and which single event upsets (SEUs) are critical to the program execution of the computer system at the cycle accurate instruction set simulation (ISS) level. The soft-error model is capable of estimating reliability of a computer system that has several memory hierarchies with it and finding which memory module is vulnerable in the computer system. Reliability estimation helps system designers apply reliable design techniques to vulnerable part of their design. The experimental results have shown that the usage of the soft-error model achieved more accurate reliability estimation than conventional approaches. The experimental results demonstrate that reliability of computer systems depends on not only soft error rates (SERs) of memories but also the behavior of software running in computer systems.