Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade

Junichi AKITA  Hiroaki TAKAGI  Keisuke DOUMAE  Akio KITAGAWA  Masashi TODA  Takeshi NAGASAKI  Toshio KAWASHIMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.10   pp.1869-1875
Publication Date: 2007/10/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.10.1869
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Image Sensor/Vision Chip
Keyword: 
line-of-sight (LoS),  saccade,  vision chip,  column-parallel processing,  

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Summary: 
Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.