A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library

Yasuhiro TAKAHASHI  Toshikazu SEKINE  Michio YOKOYAMA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E90-A   No.7   pp.1376-1383
Publication Date: 2007/07/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.7.1376
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Hilbert transformer,  multiplierless,  FIR filter,  multiple constant multiplication (MCM),  canonic signed digit (CSD),  

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This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm2. The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.