IEICE Trans - Adaptive Low-Error Fixed-Width Booth Multipliers

Adaptive Low-Error Fixed-Width Booth Multipliers

Min-An SONG  Lan-Da VAN  Sy-Yen KUO

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E90-A   No.6   pp.1180-1187
Publication Date: 2007/06/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.6.1180
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Circuit Theory
Keyword:
digital signal processing,  fixed-width Booth multiplier,  VLSI,

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Summary:
In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.