An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model

Wen-Tsan HSIEH
Chi-Chia YU
Chien-Nan Jimmy LIU
Yi-Fang CHIU

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E90-A    No.5    pp.1038-1044
Publication Date: 2007/05/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.5.1038
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
memory power model,  scalable model,  lib format,  

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Embedded memories have been used extensively in modern SoC designs. In order to estimate the power consumption of an entire design correctly, an accurate memory power models are needed. However, the memory power model that is commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effects with scaling capability. The proposed approach is very useful to be combined with the memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into the existing power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.

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