Synthesis Method of All Low-Voltage CMOS Instantaneous-Companding Log Domain Integrators

Ippei AKITA  Kazuyuki WADA  Yoshiaki TADOKORO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E90-A   No.2   pp.339-350
Publication Date: 2007/02/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.2.339
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
low-supply voltage,  integrators,  instantaneous companding,  log domain,  topological optimization,  

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This paper proposes a synthesis method of all low-voltage CMOS instantaneous-companding log domain integrators. The method is based on the exhaustive search of all low-voltage CMOS instantaneous-companding log domain integrators. All the integrators are derived from a general block diagram. A function of each block can be realized by any of a family of circuits and elemental circuits chosen from such families are combined to build an integrator. It is clarified that each family contains a few circuit topologies. All topologies of integrators including new ones are obtained from combinational procedure. Comparing characteristics of all generated integrators, ones satisfying required performances are found out.