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High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC
Chun-Lung HSU Mean-Hom HO
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E90-A
No.12
pp.2818-2825 Publication Date: 2007/12/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.12.2818
Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: VLSI, motion estimation, VBSD, H.264/AVC,
Full Text: PDF(3MB)>>
Summary:
This paper proposes a flexible VLSI architecture design for motion estimation in H.264/AVC using a high-efficiency variable block-size decision (VBSD) approach. The proposed VBSD approach can perform a full motion search on integrating the 4 4 block sizes into 4 8, 8 4, 8 8, 8 16, 16 8, or 16 16 block sizes and then appropriately select the optimal modes for motion compensation operating. In other words, the proposed architecture based on the VBSD approach can effectively reduce the encoding time of the motion estimation by dealing with different block sizes under 16 16 searching range. Using the TSMC 0.18-µm CMOS technology, the proposed architecture has been successfully realized. Simulation and verification results show that the proposed architecture has significant bit-rate reduction and small PSNR degradation. Also, the physical chip design revealed that the maximum frame rate of this work can process 704 fps with QCIF (176 144), 176 fps with CIF (352 288) and 44 fps with 4CIF (704 576) video resolutions under lower gate counts and higher working frequency.
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