
For FullText PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.

A Fast ProbabilityBased Algorithm for Leakage Current Reduction Considering Controller Cost
TsungYi WU JrLuen TZENG
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E90A
No.12
pp.27182726 Publication Date: 2007/12/01 Online ISSN: 17451337
DOI: 10.1093/ietfec/e90a.12.2718 Print ISSN: 09168508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: leakage current reduction, minimum leakage vector, minimum leakage vector controller, low power design,
Full Text: PDF>>
Summary:
Because the leakage current of a digital circuit depends on the states of the circuit's logic gates, assigning a minimum leakage vector (MLV) for the primary inputs and the flipflops' outputs of the circuit that operates in the sleep mode is a popular technique for leakage current reduction. In this paper, we propose a novel probabilitybased algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn vector controller, our technique can take this overhead into account. Ignoring this overhead during solution space exploration may bring a side effect that is misrecognizing a nonoptimal solution as an optimal one. Experimental results show that our heuristic algorithm can reduce the leakage current up to 59.5% and can find the optimal solutions on most of the small MCNC benchmark circuits. Moreover, the required CPU time of our probabilitybased program is significantly less than that of a random search program.


