A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information

Chung-chi LIN  Ming-hwa SHEU  Huann-keng CHIANG  Chih-Jen WEI  Chishyan LIAW  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E90-A   No.11   pp.2575-2583
Publication Date: 2007/11/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.11.2575
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Image
de-interlacing,  progressive scan,  scene change,  VLSI,  

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Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-µm CMOS technology process. The total gate count is 30114 and its layout area is about 710 710-µm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.