An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits

Tetsuya ASAI
Tetsuya HIROSE
Yoshihito AMEMIYA

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E90-A    No.10    pp.2108-2115
Publication Date: 2007/10/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.10.2108
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Neuron and Neural Networks
neuromorphic analog integrated circuits,  pulse density modulation,  noise shaping,  subthreshold CMOS circuits,  

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We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhibited noise-shaping properties, and signal-to-noise ratio (SNR) of the network was improved by 7.9 dB compared with that of the uncoupled network as a result of noise shaping.