Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm

Ryoichiro ATONO  Shuichi ICHIKAWA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E89-D   No.7   pp.2301-2305
Publication Date: 2006/07/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e89-d.7.2301
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: VLSI Systems
Keyword: 
FPGA,  custom circuit,  partial evaluation,  specialization,  cryptography,  embedded system,  

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Summary: 
If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.