An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors

CheolHong KIM  SungWoo CHUNG  ChuShik JHON  

IEICE TRANSACTIONS on Information and Systems   Vol.E89-D    No.4    pp.1450-1458
Publication Date: 2006/04/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e89-d.4.1450
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer Systems
instruction cache,  partitioned cache,  low power design,  dynamic energy,  embedded processor,  

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Energy efficiency of cache memories is crucial in designing embedded processors. Reducing energy consumption in the instruction cache is especially important, since the instruction cache consumes a significant portion of total processor energy. This paper proposes a new instruction cache architecture, named Partitioned Instruction Cache (PI-Cache), for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less power-consuming) sub-caches. When the proposed PI-Cache is accessed, only one sub-cache is accessed by utilizing the temporal/spatial locality of applications. In the meantime, other sub-caches are not accessed, leading to dynamic energy reduction. The PI-Cache also reduces dynamic energy consumption by eliminating the energy consumed in tag lookup and comparison. Moreover, the performance gap between the conventional instruction cache and the proposed PI-Cache becomes little when the physical cache access time is considered. We evaluated the energy efficiency by running a cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Simulation results show that the PI-Cache improves the energy-delay product by 20%-54% compared to the conventional direct-mapped instruction cache.