Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch

Yoshiyuki NAKAMURA  Thomas CLOUQUEUR  Kewal K. SALUJA  Hideo FUJIWARA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E89-D   No.3   pp.1165-1172
Publication Date: 2006/03/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e89-d.3.1165
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
BIST,  fault diagnosis,  error identification,  at-speed test,  low speed tester,  

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Summary: 
In this paper, we provide a practical formulation of the problem of identifying all error occurrences and all failed scan cells in at-speed scan based BIST environment. We propose a method that can be used to identify every error when the circuit test frequency is higher than the tester frequency. Our approach requires very little extra hardware for diagnosis and the test application time required to identify errors is a linear function of the frequency ratio between the CUT and the tester.