Accelerating Verification with Reusable Testbench

Jungbo SON  Hae-Wook CHOI  Sin-Chong PARK  

IEICE TRANSACTIONS on Information and Systems   Vol.E89-D   No.2   pp.853-856
Publication Date: 2006/02/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e89-d.2.853
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Dependable Computing
verification,  testbench,  reuse,  Aptix,  Celaro,  

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The increased complexity in system design has brought an explosive growth in functional verification time. Thus, many verification methodologies have been proposed to reduce it. One of them is the co-emulation method in which the hardware accelerator and software simulator work together. This paper presents an effective testbench architecture for accelerated verification and reuse of parts of the testbench in co-emulation. The testbench is divided into a synthesizable part which can be hardware accelerated and a non-synthesizable part which remains on the software simulator. The split blocks of the testbench can be reused in other test environments. Experiments with real world systems show that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment.