Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time

Yu HU  Yinhe HAN  Xiaowei LI  Huawei LI  Xiaoqing WEN  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E89-D   No.10   pp.2616-2625
Publication Date: 2006/10/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e89-d.10.2616
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
compression,  run-length coding,  random access scan,  power dissipation,  test application time,  

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Summary: 
LSI testing is critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-testability technique for LSI design and testing, there is a strong need to reduce the test data Volume, scan-in Power dissipation, and test application Time (VPT) of full-scan testing. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme to tackle all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3%, and 85.5% reduction effects in test data volume, average scan-in power dissipation, peak scan-in power dissipation, and test application time, respectively.