A Test Structure to Analyze Highly-Doped-Drain and Lightly-Doped-Drain in CMOSFET

Takashi OHZONE
Kazuhiko OKADA
Kiyotaka KOMOKU
Toshihiro MATSUDA
Hideyuki IWATA

IEICE TRANSACTIONS on Electronics   Vol.E89-C    No.9    pp.1351-1357
Publication Date: 2006/09/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.9.1351
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
CMOSFET,  LDD-type,  source/drain-resistance,  sheet resistance,  

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A test structure to separately measure sheet resistances of highly-doped-drain (HDD) and lightly-doped-drain (LDD) in LDD-type CMOSFETs with various gate spaces S having sub-100 nm sidewalls was proposed. From the reciprocal of source/drain-resistance R-1 versus S characteristics, the sheet resistance ρH of the high-conductive-region (HCR) corresponding to HDD and the approximate width WLC of the low-conductive-region (LCR) corresponding to LDD could be estimated. Both of ρH and WLC for p- and n-MOS devices were scarcely dependent on the gate voltage. The sidewall-width difference of 40 nm could be sufficiently detected by using the test structure with the S pitch of about 60 nm. The R-1 versus S characteristics showed the unstable resistance variations in the narrow S region less than 0.3 µm, which corresponded to the minimum S for the process used for the test device fabrication and suggested that various micro-loading effects seriously affected on the characteristics.