Novel Fabrication Technology for High Yield Sub-100-nm-Gate InP-Based HEMTs

Hideaki MATSUZAKI  Takashi MARUYAMA  Takatomo ENOKI  Masami TOKUMITSU  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.7   pp.949-953
Publication Date: 2006/07/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.7.949
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM2005)
Category: Millimeter-Wave Devices
Keyword: 
HEMT,  InP,  InGaAs,  InAlAs,  lattice-matched,  current gain cutoff frequency,  

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Summary: 
A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of RS. The average current-gain-cutoff-frequency (fT) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average fT of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.