For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
microcontroller, RISC, low-latency, interrupt response time, smaller code size,
Full Text: PDF>>
A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360 MIPS/400MFLOPS/200 MHz core--based on the Harvard bus architecture--uses 0.13/0.15-µm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.