A Technique to Reduce Power Consumption for a Linear Transconductor

Fujihiko MATSUMOTO  Isamu YAMAGUCHI  Akira YACHIDATE  Yasuaki NOGUCHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.6   pp.814-818
Publication Date: 2006/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.6.814
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
analog integrated circuits,  MOS transistor,  linear transconductor,  low power technique,  

Full Text: PDF(456.2KB)>>
Buy this Article




Summary: 
A new method to reduce power consumption of a linear transconductor is proposed in this paper. The minimum tail current for the operation of the transconductor is supplied by a new current source circuit. The proposed circuit is based on a dynamic biasing current technique. Results of SPICE simulation show that the proposed technique is very effective to reduce power consumption of the transconductor.