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A Technique to Reduce Power Consumption for a Linear Transconductor
Fujihiko MATSUMOTO Isamu YAMAGUCHI Akira YACHIDATE Yasuaki NOGUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
analog integrated circuits, MOS transistor, linear transconductor, low power technique,
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A new method to reduce power consumption of a linear transconductor is proposed in this paper. The minimum tail current for the operation of the transconductor is supplied by a new current source circuit. The proposed circuit is based on a dynamic biasing current technique. Results of SPICE simulation show that the proposed technique is very effective to reduce power consumption of the transconductor.