An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity

Koichiro NOGUCHI  Makoto NAGATA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.6   pp.761-768
Publication Date: 2006/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.6.761
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
signal integrity,  substrate crosstalk,  delay variation,  on-chip monitor,  

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Summary: 
A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device geometry, followed by a current-mode sample and a hold circuit that is connected to a shared current output bus. A prototype signal monitor circuit demonstrated a 1.1-GHz effective bandwidth for 1.0-V full-swing digital signals in a 90-nm CMOS technology, where the monitor used 2.5-V I/O CMOS transistors and occupied a 30 µm120 µm silicon area. We also showed that such signal monitor circuits can be tailored to sense of power-supply, ground, as well as full-swing logic signal wirings, and form an array with a single current output. Therefore, an on-chip multi-channel signal monitor enables multiple-points as well as multiple-voltage domain waveform acquisition for the purpose of the in-depth study of digital signal integrity.