True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalers

Sheng-Che TSENG  Chinchun MENG  Wei-Yu CHEN  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.6   pp.725-731
Publication Date: 2006/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.6.725
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
prescaler,  divide-by-3,  50% duty cycle,  SiGe BiCMOS,  

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Summary: 
Four 50% duty-cycle divide-by-3 prescalers--positively/ negatively triggered sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers--are designed based on the current switchable D flip-flops and discussed in this paper. The positively triggered SSH and SHH prescalers are fabricated using the 0.35-µm SiGe BiCMOS technology and measured by the real-time oscilloscope and the spectrum analyzer. The SHH prescaler is our proposed structure and demonstrated in this paper. According to the measurement results, under the condition of the same input power, its maximum operation frequency is twice as high as that of the SSH prescaler thanks to better signal synchronization. At 2.7 V supply, the SSH prescaler operates from 500 MHz to 2 GHz as the SHH prescaler performs from 1 GHz to 3.4 GHz. The input sensitivity level of both structures is about -5 dBm, while the maximum output power is also about -5 dBm. The core current consumption is 4.538 mA and 4.258 mA for the SSH and SHH prescalers, respectively.