Instruction Based Synthesizable Testbench Architecture

Ho-Seok CHOI  Hae-Wook CHOI  Sin-Chong PARK  

IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.5   pp.653-657
Publication Date: 2006/05/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.5.653
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
verification,  testbench,  emulation,  instruction,  

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This paper presents a synthesizable testbench architecture based on a defined instruction for standalone mode verification. A set of instructions describes transitions of a signal. The set of instructions can be changed easily to describe different signal transitions by loading the different set of instructions on emulator's memory. The proposed testbench enables a fast emulation and increases flexibility and reusability by using an instruction set. To prove the performance of instruction based synthesizable testbench, we verified Bluetooth and IEEE 802.11a PHY baseband systems and compared their performance with those of co-sim mode and modified co-sim mode emulation.