A Statistical Quality Model for Delay Testing

Yasuo SATO  Shuji HAMADA  Toshiyuki MAEDA  Atsuo TAKATORI  Seiji KAJIHARA  

IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.3   pp.349-355
Publication Date: 2006/03/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.3.349
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Signal Integrity and Variability
delay testing,  quality model,  defect distribution,  

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In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.