Variability: Modeling and Its Impact on Design

Hidetoshi ONODERA  

IEICE TRANSACTIONS on Electronics   Vol.E89-C    No.3    pp.342-348
Publication Date: 2006/03/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.3.342
Print ISSN: 0916-8516
Type of Manuscript: Special Section INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
variability,  within-die variability,  die-to-die variability,  statistical design,  

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As the technology scaling approaching nano-scale region, variability in device performance becomes a major issue in the design of integrated circuits. Besides the growing amount of variability, the statistical nature of the variability is changing as the progress of technology generation. In the past, die-to-die variability, which is well managed by the worst case design technique, dominates over within-die variability. In present and the future, the amount of within-die variability is increasing and it casts a challenge in design methodology. This paper first shows measured results of variability in three different processes of 0.35, 0.18, and 0.13 µm technologies, and explains the above mentioned trend of variability. An example of modeling for the within-die variability is explained. The impact of within-die random variability on circuit performance is demonstrated using a simple numerical example. It shows that a circuit that is designed optimally under the assumption of deterministic delay is now most susceptible to random fluctuation in delay, which clearly indicates the requirement of statistical design methodology.