A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology

Noriyuki MIURA
Takayasu SAKURAI
Tadahiro KURODA

IEICE TRANSACTIONS on Electronics   Vol.E89-C    No.3    pp.320-326
Publication Date: 2006/03/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.3.320
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Interface and Interconnect Techniques
inductive coupling,  wireless superconnect,  3D-stacked chips,  low power,  high bandwidth,  

Full Text: PDF(904KB)>>
Buy this Article

A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm2 will be obtained.