Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies

Hirotaka TAMURA  Masaya KIBUNE  Hisakatsu YAMAGUCHI  Kouichi KANDA  Kohtaroh GOTOH  Hideki ISHIDA  Junji OGAWA  

IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.3   pp.300-313
Publication Date: 2006/03/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.3.300
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
CMOS,  high-speed I/O,  interface,  sub-100 nm,  

Full Text: PDF>>
Buy this Article

The paper provides an overview of the circuit techniques for CMOS high-speed I/Os, focusing on the design issues in sub-100 nm standard CMOS. First, we describe the evolution of CMOS high-speed I/O since it appeared in mid 90's. In our view, the surge in the I/O bandwidth we experienced from the mid 90's to the present was driven by the continuous improvement of the CMOS IC performance. As a result, CMOS high-speed I/O has covered the data rate ranging from 2.5 Gb/s to 10 Gb/s, and now is heading for 40 Gb/s and beyond. To meet the speed requirements, an optimum choice of the transceiver architecture and its building blocks are crucial. We pick the most critical building blocks such as the decision circuit and the multiplexors and give detailed explanation of their designs. We describe the low-voltage operation of the high-speed I/O in view of reducing the power consumption. An example of a 90-nm CMOS 2.5 Gb/s transceiver operating off a 0.8 V power supply will be described. Operability at 0.8 V ensures that the circuits will not become obsolescent, even below the 60 nm process node.