Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core

Tetsuya YAMADA  Masahide ABE  Yusuke NITTA  Kenji OGURA  Manabu KUSAOKE  Makoto ISHIKAWA  Motokazu OZAWA  Kiwamu TAKADA  Fumio ARAKAWA  Osamu NISHII  Toshihiro HATTORI  

IEICE TRANSACTIONS on Electronics   Vol.E89-C    No.3    pp.287-294
Publication Date: 2006/03/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.3.287
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Low Power Techniques
embedded processor,  clock,  gated clock,  flip-flop,  

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A low-power SuperHTM embedded processor core, the SH-X2, has been designed in 90-nm CMOS technology. The power consumption was reduced by using hierarchical fine-grained clock gating to reduce the power consumption of the flip-flops and the clock-tree, synthesis and a layout that supports the implementation of the clock gating, and several-level power evaluations for RTL refinement. With this clock gating and RTL refinement, the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using a Renesas low-power process with a lowered voltage. Its performance-power efficiency was 25% better than that of a 130-nm-process SH-X.