For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
10 GHz Low-Noise Low-Power Monolithic Integrated VCOs in Digital CMOS Technology
Zheng GU Andreas THIEDE
IEICE TRANSACTIONS on Electronics
Publication Date: 2006/01/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
oscillator, on-chip inductor, MOS varactor, differential structure,
Full Text: PDF(758.9KB)>>
This paper presents the design of low-power low-noise 10 GHz CMOS monolithic integrated LC VCOs suitable for data clock recovery architectures in optical receivers of SDH (STM-64) and SONET (OC-192). Optimizations of device parameters and passive components are given in detail. For passive components, differential and single-ended inductor structures as well as MOS varactors with and without lightly doped drain/source (LDD) implantation have been investigated. The VCOs implemented in a 0.18 µm process demonstrate the single-side-band phase noise of as low as -107 dBc/Hz at 1 MHz offset and 21% tuning range while consuming only 7 mW under 1.8 V supply.