IEICE Trans - 10 GHz Low-Noise Low-Power Monolithic Integrated VCOs in Digital CMOS Technology

10 GHz Low-Noise Low-Power Monolithic Integrated VCOs in Digital CMOS Technology

Zheng GU
Andreas THIEDE

Publication
IEICE TRANSACTIONS on Electronics Vol.E89-C No.1 pp.88-93
Publication Date: 2006/01/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.1.88
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword:
oscillator, on-chip inductor, MOS varactor, differential structure,

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Summary:
This paper presents the design of low-power low-noise 10 GHz CMOS monolithic integrated LC VCOs suitable for data clock recovery architectures in optical receivers of SDH (STM-64) and SONET (OC-192). Optimizations of device parameters and passive components are given in detail. For passive components, differential and single-ended inductor structures as well as MOS varactors with and without lightly doped drain/source (LDD) implantation have been investigated. The VCOs implemented in a 0.18 µm process demonstrate the single-side-band phase noise of as low as -107 dBc/Hz at 1 MHz offset and 21% tuning range while consuming only 7 mW under 1.8 V supply.