A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates

Masanori HARIYAMA  Sho OGATA  Michitaka KAMEYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.11   pp.1655-1661
Publication Date: 2006/11/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.11.1655
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
time-multiplexed FPGA,  dynamically reconfigurable architecture,  DPGA,  bit-serial architecture,  

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Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause a large overhead in area when a number of contexts are used. To overcome the overhead, a fine-grained MC-FPGA architecture using a floating-gate-MOS functional pass gate (FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The test chip is designed using a 0.35 µm CMOS-EPROM technology. The transistor count of the proposed multi-context switch (MC-switch) is reduced to 13% in comparison with SRAM-based one. The total area of the proposed MC-FPGA is reduced to about 56% of that of a conventional SRAM-based MC-FPGA.