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Systematic Interpretation of Redundant Arithmetic Adders in Binary and MultipleValued Logic
Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI
Publication
IEICE TRANSACTIONS on Electronics
Vol.E89C
No.11
pp.16451654 Publication Date: 2006/11/01
Online ISSN: 17451353
DOI: 10.1093/ietele/e89c.11.1645
Print ISSN: 09168516 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: datapaths, arithmetic circuits, addition algorithms, number systems, multiplevalued logic,
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Summary:
This paper presents an algorithmlevel interpretation of fast adder structures in binary/multiplevalued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to describe and analyze addition algorithms at various levels of abstraction. A highlevel CTD represents a network of coarsegrained components associated with multiplevalued logic devices, while a lowlevel CTD represents a network of primitive components directly mapped onto binary logic devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a highlevel CTD into lowlevel CTDs. This paper demonstrates the interpretation of redundant arithmetic adders based on CTDs. We first introduce an extension of CTDs to represent possible redundant arithmetic adders with limited carry propagation. Using the extended version of CTDs, we can classify the conventional adder structures including those using emerging devices into three types in a systematic way.

