Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture

Toru SHIMIZU  Masami NAKAJIMA  Masahiro KAINAGA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.11   pp.1512-1518
Publication Date: 2006/11/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.11.1512
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
massively parallel processor,  SIMD,  fine-grained ALU,  wideband bus,  

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Summary: 
This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40 GOPS of 16-bit fixed-point additions at 200 MHz clock frequency and 250 mW power dissipation. In addition, 1 M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1 mm2 in 90 nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs.