For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Low Latency and Memory Efficient Viterbi Decoder Using Modified State-Mapping Method
Sang-Ho SEO Hae-Wook CHOI Sin-Chong PARK
IEICE TRANSACTIONS on Communications
Publication Date: 2006/04/01
Online ISSN: 1745-1345
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Fundamental Theories for Communications
Viterbi decoder, register exchange, trace back, latency, resource usage,
Full Text: PDF(977.8KB)>>
In this paper, a new implementation of the Viterbi decoder is proposed. The Modified State-Mapping VD algorithm combines the TB algorithm with the RE algorithm. By updating the starting point of the state for each memory bank, and by using Trace Back and Trace Forward information, LIFO (Last Input First Output) operation can be eliminated, which reduces the latency of the TB algorithm and decreases the resource usage of the RE algorithm. When the memory unit is 3, the resource usage is 13184 bits and the latency is 54 clocks. The latency of the proposed algorithm is 25% smaller than the MRE algorithm and 50% smaller than the k-pointer even TB algorithm. In addition, resource usage is 50% smaller than the RE algorithm. The resource usage is a little larger than that of the MRE algorithm for the small value of k, but it becomes smaller after k is larger than 16.