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Low Complexity Bit-Parallel Squarer for GF(2n) Defined by Irreducible Trinomials
Sun-Mi PARK Ku-Young CHANG
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/09/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Algorithms and Data Structures
finite field arithmetic, bit-parallel squarer, trinomial, shifted polynomial basis,
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We present a bit-parallel squarer for GF(2n) defined by an irreducible trinomial xn +xk +1 using a shifted polynomial basis. The proposed squarer requires TX delay and at most n/2 XOR gates, where TX is the delay of one XOR gate. As a result, the squarer using the shifted polynomial basis is more efficient than one using the polynomial basis except for k=1 or n/2.