Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding

Myung-Suk BYEON
Yil-Mi SHIN
Yong-Beom CHO

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A    No.6    pp.1744-1745
Publication Date: 2006/06/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.6.1744
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
H.264 encoding,  image compression,  motion estimation,  hardware architecture,  

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Summary: 
This paper describes the efficiency of VLSI architecture for UMHexagonS (hybrid Unsymmetrical cross Multi Hexagon grid Search) matching algorithm. This algorithm is used for ME (Motion Estimation) of H.264/AVC video compression standard. The UMHexagonS is called a hybrid algorithm since it uses different kinds of searching patterns. VLSI architecture based on UMHexagonS is designed to provide a good tradeoff between gate sizes and high throughput. We implemented this architecture with about 309 K gates and 1/1792 throughput [block/cycle] for a search range of 16 and 44 macro blocks using synthesizable Verilog HDL.

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