An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

Seonyoung LEE  Kyeongsoon CHO  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A   No.6   pp.1736-1739
Publication Date: 2006/06/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.6.1736
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
H.264/AVC,  deblocking filter,  SoC architecture,  platform-based design,  

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Summary: 
We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.