A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source

Kazuhiro SHOUNO  Tasuku HORI  Yukio ISHIBASHI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A   No.6   pp.1533-1539
Publication Date: 2006/06/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.6.1533
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
CMOS,  analog,  transconductor,  multiplier,  mobility,  

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This paper proposes a linearized multiplier using the MOS transistors. The proposed circuit can be realized by adding two voltage shifters and some current mirrors to the conventional circuit. Especially, these additional voltage shifters can be saved when the proposed circuit is used as a transconductor. The proposed circuit is driven by a controlled tail current source. A technique to reduce the effect of the mobility reduction is proposed. First, the output current of the conventional transconductor is analytically derived and its problem is pointed out. Secondly, the proposed circuit is shown. The proposed method is accomplished by taking the mobility reduction into account. The validity of the proposed method is confirmed through both of Spice simulation and experiment. Finally, the proposed circuit is fabricated in the 1.2 µm CMOS process. The second-order and the third-order distortions are about -55 dB and -64 dB, respectively for a 0.5 Vp-p sinusoidal input signal.