All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter

Mitsutoshi YAHARA  Kuniaki FUJIMOTO  Hirofumi SASAKI  Takashi SHIBUYA  Yoshinori HIGASHI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A   No.6   pp.1527-1532
Publication Date: 2006/06/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.6.1527
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
PLL,  jitter,  delay clock,  lock-in range,  digital,  

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This paper proposes a new all digital dividing ratio changeable phase locked loop (D-DCPLL) using delay clock pulse that exhibits low output jitter characteristics compared with the conventional DCPLL. This is achieved by employing the delay clock pulse generated from the ring oscillator for the standard clock controlling the loop. This output jitter is always constant regardless of the frequency fluctuation of the delay clock, and the fluctuation coefficient has little effect on the output jitter. This circuit can expand the upper bound frequency of the lock-in range compared with conventional DCPLL when the permissible output jitter is identical. Furthermore, the proposed D-DCPLL can obtain an initial pull-in in one period of the input signal and the multiplication output signal of the constant pulse interval can be obtained by using the remainder control circuit.